[Market Memo] Hot Summer Topics

Irrational Analysis is heavily invested in the semiconductor industry.

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Disjoint note on some (mostly) unrelated ideas.

Applied Materials DRAM and Advanced Packaging Master Class

“Master Class” == technical marketing event

It was very well done and I enjoyed it a lot. Fair warning, I am a material science and process technology tourist. However, AMAT appears to be an optics tourist lol. You will see what I mean.

Good overview. Note the very tall capacitor. This is the main delta between DRAM and logic nodes.

EUV intensity is indeed going way up in DRAM. This is one reason I own ASML in the long only book. AMAT is arguing that this trend also benefits them due to stricter etch requirements.

Another argument is that AMAT is bringing SiGe Epi to DRAM world. Sure this seems believable and valuable.

Array and periphery disaggregation in DRAM seems like a stretch. At the very least far away. A subset of NAND world (Sandisk+Kioxia) has started to do this. Unsure if DRAM world will adopt this technology anytime soon.

Skipping vertical cell transistor and 3D DRAM sections as that stuff is far away and speculative.

I would like to know what the hell AMAT is smoking. 0.05 pj/bit for CPO? LOL

SiPho CPO is 2-3 pj/bit ideally. VCSEL CPO is 1 pj/bit.

Fundamentally, if you ignore everything else (laser, PIC heaters, driver) a typical SiPho CPO system will have hybrid bonds and TSV in the datapath. Applied Materials bullshit numbers on same slide imply CPO should be 0.6 pj/bit at a physical interface level. Nonsense numbers.

Ok well thinner DRAM dies means hybrid bonding pushed out. AMAT wins either way I guess but perhaps this is not the message they want to send given their stake in BESI.

Idiots. The laser is 99% of the time NOT IN THE PIC. Do some research next time this is embarrassing.

Waveguides do not go vertical. To make light go up, you use a grading coupler. Somehow the AMAT tourist clowns who made this slide depicted fiber attach in the wrongest way possible. Vertical waveguide into an edge coupler that somehow has z-axis angle tolerance as well.

Ok so eBeam beats optical inspection. What about Rigaku x-ray inspection? Someone go as AMAT IR about this and send me your notes I am curious.

Taking a first pass at their S-1. If anyone has more info please send it my way via email.

Conveniently left Bloom out of the comparisons.

Sigh the story seems to be recurring service revenues. Yay something I can’t properly think through.

Ok fuck this the S-1 has no useful information. Time to go to patents.

They appear to have one patent. It is for a engine with a tall vertical cooling stack.

I have had a virulent hatred of HBF (high-bandwidth flash) ever since Sandisk presented the idea in their investor day. So before the spinoff from WD.

Several have pushed back and I would like to thank these people for providing useful feedback.

Most of my opposition was due to endurance concerns. I assumed HBF was going to use TLC or QLC. The people who pushed back tell me SLC is going to be used.

Using SLC eliminates most of my concerns regarding HBF viability. The one remaining issue (big problem…) is digital logic integration.

NAND needs a lot of fancy math to perform at it’s best. These algos typically run on a dedicated logic controller. In the case of HBF, this logic needs to be integrated into the base die. Space will be tight but it seems doable. What concerns me is heat. The logic base die of a HBF stack is gona kick out a lot of heat. Likely on the order of 10 watts. Sandisk and SK Hynix (the two companies working on HBF) have a difficult problem to solve and I see no public evidence of progress on this front.

Keeping an eye on this space but for now, softening stance from “I hate HBF” to “it could work but thermal issues need to be solved”.

Santa Clara group is pro ring modulator SiPho.

Last year Santa Clara won. The roadmap for next 2-3 years is set in stone. This is true for most of the industry. SiPho based NPO and CPO is ramping across Nvidia, Broadcom, Innolight, Eoptolink, Accelink, and AMD. Microsoft and Amazon both have committed programs. InP CW laser supply is an unmitigated disaster. Three of the entities in the above list are in a panic trying to find supply.

But this move by Ashkan is very interesting for the future. He was a part of the Santa Clara group, team ring modulator. Additionally, if you are plugged into this space, you know that Ashkan’s PhD thesis is on micro-LED tech and he publicly shit on micro-LED at a conference last year in his keynote address. It was hilarious. Avicina had a booth with a (horrific) live demo and Ashkan was just roasting micro-LED on stage as the highest profile speaker.

For now, nothing changes in terms of investment view. InP CW driven SIPho (NPO or CPO, MZI or ring) is unstoppable for the next 2-3 years and there is a crippling panic spreading. Ask around. You will quickly find out who has secured supply and who is shitting themselves.

But… VCSEL CPO just got a huge vote of confidence from someone very important. I am keeping an eye on this.

The challenge is not the VCSELs themselves. It is packaging them in a dense way with high yield. Broadcom is VCSEL king with Coherent in close second. Lumentum and Furukawa also have decent VCSEL tech. For CPO/NPO, 50G NRZ is the sweet spot in my opinion. At that data rate, the quality of the VCSEL itself is not important. What matters is the integration and packaging of VCSEL+Fibers+drivers.

Given the continued momentum of Bloom and behind-the-meter (not grid connected) power, I wonder how much reach 800V DC has. Literally how far can the transmission lines between datacenter and Bloom cells be before resistive loss kills you.

800V direct disproportionately benefits GaN and Navitas. Although it concerns me Navitas management keeps shilling the stupid “we have both GaN and SiC and this is a advantage” nonsense.

Navitas SiC is dogshit btw. I did a deep analysis or SiC and GaN across all players.

Irrational Analysis is heavily invested in the semiconductor industry.

Ok well 10AWG limit is 30A so lets go lower.

There is no reality in which these lines run at 20C so bias up resistance.

P_loss = 375*375*(pessimistic 0.4 ohm) = 56 KW loss

So… 56/300 = 18.6% transmission loss which is dogshit.

Assuming you want less than 10% transmission loss, max is 500 feet or 150 meter which is not great.

I must be missing something. If anyone has insights on high power transmission systems please send me an email.

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